1. Technical Field
Various embodiments relate to a semiconductor apparatus, and, more particularly, to a semiconductor apparatus having a plurality of chips and a plurality of channels.
2. Related Art
In order to improve semiconductor integration, 3-dimensional (3D) semiconductor structures are being used. Integration is improved by stacking and packaging a plurality of chips in a single package. Therefore, a 3D semiconductor apparatus has two or more vertically stacked chips and is able to achieve a high degree of integration in a limited space.
In a 3D semiconductor apparatus, a plurality of chips may be stacked and packaged in various ways. For example, a plurality of chips having the same structure may be stacked and coupled to each other through a wire, such as a metal line, to serve as a single semiconductor apparatus.
Under a through-silicon via (TSV) scheme, as another example, a plurality of chips may be stacked and electrically coupled using a via passing therethrough. Since a TSV-implemented semiconductor apparatus couples stacked chips using the via passing therethrough, it may efficiently reduce its package area compared to a wire-implemented semiconductor apparatus using a wire disposed on the border area of stacked chips.
Each of the plurality of chips of the semiconductor apparatus may constitute a channel. A plurality of channels may transfer different control signals and data, and the plurality of chips may independently operate.